Integrated circuit chip and method for fabricating the same

ABSTRACT

A method for fabricating an integrated circuit chip includes the steps of:  
     (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit;  
     (b) forming a die having an upper surface provided with a plurality of solder pads;  
     (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed;  
     (d) wire-bonding the solder pads to the contact pads via conductive wires;  
     (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and  
     (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to an integrated circuit chip and a methodfor fabricating the same, more particularly to an integrated circuitchip and a method for fabricating the same that can reduce productioncosts and that can increase production capacity.

[0003] 2. Description of the Related Art

[0004] Referring to FIGS. 1A to 1C, a conventional method forfabricating an integrated circuit chip is shown. As shown in FIG. 1A, adie 10 having an upper surface provided with a plurality of solder pads100 is attached to a tie bar 130 on a lead frame 13 by means of adouble-side adhesive tape 12 to fix the die 10 on the lead frame 13. Thesolder pads 100 are exposed via a bore 1300 formed in the tie bar 130,as shown in FIG. 1D. Referring to FIG. 1B, each of the solder pads 100is connected electrically to a respective lead 131 of the lead, frame 13via known wire bonding,techniques by means of a conductive wire 14 thatextends through the bore 1300. Referring to FIG. 1C, a plasticprotective layer 15 is used to encapsulate the die 10 and a portion ofthe lead frame 13 to form an integrated circuit chip.

[0005] The following are some of the drawbacks of the conventionalmethod for fabricating an integrated circuit chip:

[0006] 1. The aforesaid method needs different kinds of lead frames fordifferent kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on.Thus, at least one mold is prepared for each customer, therebyincreasing costs.

[0007] 2. In the aforesaid method, double-side adhesive tape is neededto secure the die on the tie bar, thereby increasing the fabricatingcosts.

[0008] 3. In the aforesaid method, it will take a long time to form themolds for the lead frames, thereby affecting the ability ofmanufacturers to compete.

SUMMARY OF THE INVENTION

[0009] Therefore, the main object of the present invention is to providean integrated circuit chip and a method for fabricating the same whichcan overcome the drawbacks associated with the aforesaid prior art.

[0010] According to this invention, a method for fabricating anintegrated circuit chip comprises:

[0011] (a) forming a circuit board unit with a die-receiving cavity, anda plurality of contact pads on a top surface of the circuit board unit;

[0012] (b) forming a die having an upper surface provided with aplurality of solder pads;

[0013] (c) placing the die in the die-receiving cavity such that thesolder pads on the die are exposed;

[0014] (d) wire-bonding the solder pads to the contact pads viaconductive wires;

[0015] (e) placing a lead frame on the circuit board unit, andconnecting leads on the lead frame to corresponding ones of the contactpads via a conductive contact layer; and

[0016] (f) forming a plastic protective layer to encapsulate the circuitboard unit and at least a portion of the lead frame.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features and advantages of the present invention willbecome apparent in the following detailed description of the preferredembodiments with reference to the accompanying drawings, of which:

[0018]FIGS. 1A to 1C are fragmentary schematic, partly sectional viewsshowing a conventional method for fabricating an integrated circuitchip.

[0019]FIG. 1D is a fragmentary top view showing a lead frame used in theconventional method for fabricating an integrated circuit chip.

[0020]FIGS. 2A to 2D are fragmentary schematic, partly sectional viewsshowing the first preferred embodiment of a method for fabricating anintegrated circuit chip of this invention.

[0021]FIG. 2E is a fragmentary top view showing a lead frame used in thefirst preferred embodiment of this invention.

[0022]FIG. 3 is a fragmentary schematic, partly sectional view showingthe second preferred embodiment of this invention.

[0023]FIG. 4 is a fragmentary schematic, partly sectional view showingthe third preferred embodiment of this invention.

[0024]FIG. 5 is a fragmentary schematic, partly sectional view showingthe fourth preferred embodiment of this invention.

[0025]FIG. 6 is a fragmentary schematic, partly sectional view showingthe fifth preferred embodiment of this invention.

[0026]FIG. 7 is a fragmentary schematic, partly sectional view showingthe sixth preferred embodiment of this invention.

[0027]FIG. 8 is a fragmentary schematic, partly sectional view showingthe seventh preferred embodiment of this invention.

[0028]FIG. 9 is a fragmentary top view showing the seventh preferredembodiment of this invention. FIG. 10 is a fragmentary schematic, partlysectional view showing the eighth preferred embodiment of thisinvention.

[0029]FIG. 11 is a fragmentary schematic, partly sectional view showingthe ninth preferred embodiment of this invention.

[0030]FIG. 12 is a fragmentary schematic, partly sectional view showingthe tenth preferred embodiment of this invention. FIG. 13 is afragmentary schematic, partly sectional view showing the eleventhpreferred embodiment of this invention.

[0031]FIG. 14 is a fragmentary schematic, partly sectional view showingthe twelfth preferred embodiment of this invention.

[0032]FIG. 15 is a fragmentary schematic, partly sectional view showingthe thirteenth preferred embodiment of this invention.

[0033]FIG. 16 is a fragmentary schematic, partly sectional view showingthe fourteenth preferred embodiment of this invention.

[0034]FIG. 17 is a fragmentary schematic, partly sectional view showingthe fifteenth preferred embodiment of this invention.

[0035]FIG. 18 is a fragmentary schematic, partly sectional view showingthe sixteenth preferred embodiment of this invention.

[0036]FIG. 19. is a fragmentary schematic, partly sectional view showingthe seventeenth preferred embodiment of this invention.

[0037]FIG. 20 is a fragmentary schematic, partly sectional view showingthe eighteenth preferred embodiment of this invention.

[0038]FIG. 21 is a fragmentary schematic, partly sectional view showingthe nineteenth preferred embodiment of this invention.

[0039]FIG. 22 is a fragmentary schematic, partly sectional view showingthe twentieth preferred embodiment of this invention.

[0040]FIG. 23 is a fragmentary schematic, partly sectional view showingthe twenty-first preferred embodiment of this invention.

[0041]FIG. 24 is a fragmentary schematic, partly sectional view showingthe twenty-second preferred embodiment of this invention.

[0042]FIG. 25 is a fragmentary schematic, partly sectional view showingthe twenty-third preferred embodiment of this invention.

[0043]FIG. 26 is a fragmentary schematic, partly sectional view showingthe twenty-fourth preferred embodiment of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Before the present invention is described in greater detail, itshould be noted that like elements are denoted by the same referencenumerals throughout the disclosure.

[0045] Referring to FIGS. 2A to 2E, according to. the first preferredembodiment of this invention, an integrated circuit chip includes acircuit board unit 2, a die 3, a plurality of conductive wires 4, a leadframe 5, a conductive contact layer 51, and a plastic protective layer6. Referring to FIGS. 2A and 2B, the circuit board unit 2 has a bottomsurface 200 formed with a die-receiving cavity 20, a top surface 210formed with a bore 21 to access the die-receiving cavity 20, and aplurality of contact pads 22 on the top surface 210 of the circuit boardunit 2. The die 3 has an upper surface 300 provided with a plurality ofsolder pads 30. The die 3 is placed inside the die-receiving cavity 20such that the solder pads 30 are exposed via the bore 21 in the circuitboard unit 2. Referring to FIG. 2C, the conductive wires 4 extendthrough the bore 21 and wire-bond the solder pads 30 to the contact pads22. Referring to FIGS. 2C and 2D, the lead frame 5 is placed on top ofthe circuit board unit 2. The lead frame 5 has a plurality of leads 50.The conductive contact layer 51 is disposed between the lead frame 5 andthe circuit board unit 2 to bond the leads 50 on the lead frame 5 ontocorresponding ones of the contact pads 22. The conductive contact layer51 is formed from a silver epoxy, such as one that contains both tin andlead, or solder paste that contains tin. The plastic protective layer 6is used to encapsulate the circuit board unit 2 and at least a portionof the lead frame 5, as shown in FIG. 2E.

[0046]FIG. 3 illustrates the second preferred embodiment of thisinvention, which is based on the first preferred embodiment. In FIG. 3,unlike the first preferred embodiment shown in of FIG. 2D, the circuitboard unit 2A is further formed with a plurality of electroplated holes23 registered respectively with the contact pads 22A and extendingthrough a bottom surface of the circuit board unit 2A. The lead frame 5is placed below the circuit board unit 2A. The conductive contact layer51 is disposed between the lead frame 5 and the circuit board unit 2A tobond leads 50 on the lead frame 5 onto the electroplated holes 23 toestablish electrical connection with corresponding ones of the contactpads 22A.

[0047]FIG. 4 illustrates the third preferred embodiment of thisinvention, which is based on the first preferred embodiment. In FIG. 4,unlike the first preferred embodiment shown in FIG. 2D, the circuitboard unit 2B includes a lower circuit board 25 formed with thedie-receiving cavity 20B, and an upper circuit board 24 superimposed onthe lower circuit board 25 and formed with the bore 21B. The uppercircuit board 24 has the contact pads 22B formed on the top surfacethereof, and is further formed with first electroplated holes 240registered respectively with the contact pads 22B. The lower circuitboard 25 is formed with second electroplated holes 250 registeredrespectively with the first electroplated holes 240. Thus, circuittraces (not shown) on the bottom side of the lower circuit board 25 canbe connected to the leads 50 of the lead frame 5 via the holes 250, 240and the contact pads 22B.

[0048]FIG. 5 illustrates the fourth preferred embodiment of thisinvention, which is based on the first preferred embodiment. In FIG. 5,unlike the first preferred embodiment shown in FIG. 2D, the circuitboard unit 2C has a top surface 21C formed with the die-receiving cavity20C. The die 3 is placed in the die-receiving cavity 20C. The uppersurface 300 of the die 3 is flush with the top surface 21C of thecircuit board unit 2C.

[0049]FIG. 6 illustrates the fifth preferred embodiment of thisinvention, which is based on the fourth preferred embodiment. In FIG. 6,unlike the fourth preferred embodiment shown in FIG. 5, the circuitboard unit 2D is further formed with a plurality of electroplated holes23D registered respectively with the contact pads 22D and extendingthrough a bottom surface of the circuit board unit 2D. The lead frame 5is placed below the circuit board unit 2D. The conductive contact layer51 is disposed between the lead frame 5 and the circuit board unit 2D tobond the leads 50 on the lead frame 5 onto the electroplated holes 23Dto establish electrical connection with corresponding ones of thecontact pads 22D.

[0050]FIG. 7 illustrates the sixth preferred embodiment of thisinvention, which is based on the fourth preferred embodiment. In FIG. 7,unlike the fourth preferred embodiment shown in FIG. 5, the circuitboard unit 2E includes a lower circuit board 25E and an upper circuitboard 24E superimposed on the lower circuit board 25E and formed withthe die-receiving cavity 20E. The upper circuit board 24E has thecontact pads 22E formed on a top surface 21E thereof, and is furtherformed with first electroplated holes 240E registered respectively withthe contact pads 22E. The lower circuit board 25E is formed with secondelectroplated holes 250E registered respectively with the firstelectroplated holes 240E. Circuit traces (not shown) on the bottom sideof the lower circuit board 25E can be connected to the contact pads 22Evia the holes 250E, 240E.

[0051]FIGS. 8 and 9 illustrate the seventh preferred embodiment of thisinvention, which is based on the first preferred embodiment. In FIG. 8,unlike the first preferred embodiment shown in FIG. 2D, the circuitboard unit 2F further has opposite side portions formed with a pluralityof positioning notches 26 that correspond respectively to the contactpads 22F. Each of leads 50 on the lead frame 5 has one end inserted intoa respective one of the positioning notches 26. The conductive contaoctlayer 51 is used to bond the leads 50 on the lead frame 5 ontocorresponding ones of the contact pads 22F. The height of the resultingintegrated circuit chip can thus be reduced.

[0052]FIG. 10 illustrates the eighth preferred embodiment of thisinvention, which is based on the seventh preferred embodiment. In FIG.10, unlike the seventh preferred embodiment shown in FIG. 8, the circuitboard unit 2G includes a lower circuit board 25G formed with thedie-receiving cavity, and an upper circuit board 24G superimposed on thelower circuit board 25G and formed with the bore to access thedie-receiving cavity. The upper circuit board 24G has the contact pads22G on a top surface thereof, and is further formed with firstelectroplated holes 24OG registered respectively with the contact pads22G. The lower circuit board 25G is formed with second electroplatedholes 250G registered respectively with the first electroplated holes240G. Circuit traces (not shown) on the bottom side of the lower circuitboard 25G can be connected to the contact pads 22G via the holes 250G,240G.

[0053]FIG. 11 illustrates the ninth preferred embodiment of thisinvention, which is based on the seventh preferred embodiment. In FIG.11, unlike the seventh preferred embodiment shown in FIG. 8, the circuitboard unit 2H has a top surface 21H formed with the die-receiving cavity20H. The die 3 is placed in the die-receiving cavity 20H. An uppersurface 300 of the die 3 is flush with the top surface 21H of thecircuit board unit 2H.

[0054]FIG. 12 illustrates the tenth preferred embodiment of thisinvention, which is based on the ninth preferred embodiment. In FIG. 12,unlike the ninth preferred embodiment shown in FIG. 11, the circuitboard unit 2I includes a lower circuit board 25I and an upper circuitboard 24I superimposed on the lower circuit board 25I and formed withthe die-receiving cavity 20I. The upper circuit board 24I has thecontact pads 22I formed on a top surface 21I thereof, and is furtherformed with first electroplated holes 240I registered respectively withthe contact pads 22I. The lower circuit board 25I is formed with secondelectroplated holes 250I registered respectively with the firstelectroplated holes 240I. Circuit traces (not shown) on the bottom sideof the lower circuit board 25I can be connected to the contact pads 22Ivia the holes 250I, 240I.

[0055]FIG. 13 illustrates the eleventh preferred embodiment of thisinvention. In this embodiment, a circuit board unit 2J has a bottomsurface formed with a plurality of die-receiving cavities 20J, and a topsurface formed with a plurality of bores 21J to access a respective oneof the die-receiving cavities 20J and further formed with a plurality ofcontact pads 22J. Each of a number of dies 3 has an upper surfaceprovided with a plurality of solder pads 30. Each of the dies 3 isplaced in a respective one of the die-receiving cavities 20J such thatthe solder pads 30 on each of the dies 3 are exposed via a respectiveone of the bores 21J in the circuit board unit 2J. A plurality ofconductive wires 4 extend through the bore 21J and wire-bond the solderpads 30J to the contact pads 22J. A lead frame 5 is placed on top of thecircuit board unit 2J, and has a plurality of leads 50. A conductivecontact layer 51 is disposed between the lead frame 5 and the circuitboard unit 2J to bond the leads 50 on the lead frame 5 ontocorresponding ones of the contact pads 22J. Finally, a plasticprotective layer 6 is used to encapsulate the circuit board unit 2J andat least a portion of the lead frame 5. Thus, surface mounting steps arereduced to enhance the production capacity.

[0056]FIG. 14 illustrates the twelfth preferred embodiment of thisinvention, which is based on the eleventh preferred embodiment. In FIG.14, unlike the eleventh preferred embodiment shown in FIG. 13, thecircuit board unit 2L further has opposite side portions formed with aplurality of positioning notches 26L that correspond respectively to thecontact pads 22L. Each of the leads 50 on the lead frame 5 has one endinserted into a respective one of the positioning notches 26L. Theconductive contact layer 51 is used to bond, the leads 50 on the leadframe 5 onto corresponding ones of the contact pads 22L.

[0057]FIG. 15 illustrates the thirteenth preferred embodiment of thisinvention, which is based on the eleventh preferred embodiment. In FIG.15, unlike the eleventh preferred embodiment shown in FIG. 13, thecircuit board unit 2M has a top surface 21M formed with a plurality ofdie-receiving cavities 20M. Each of the dies 3 is placed in a respectiveone of the die-receiving cavities 20M. An upper surface 300 of each die3 is flush with the top surface 21M of the circuit board unit 2M.

[0058]FIG. 16 illustrates the fourteenth preferred embodiment of thisinvention, which is based on the thirteenth preferred embodiment. InFIG. 16, unlike the thirteenth preferred embodiment shown in FIG. 15,the circuit board unit 2N further has opposite side portions formed witha plurality of positioning notches 26N that correspond respectively tothe contact pads 22N. Each of the leads 50 on the lead frame 5 has oneend inserted into a respective one of the positioning notches 26N. Aconductive contact layer 51 is used to bond the leads 50 on the leadframe 5 onto corresponding ones of the contact pads 22N.

[0059]FIG. 17 is illustrates the fifteenth preferred embodiment of thisinvention, which is based on the second preferred embodiment. In FIG.17, unlike the second preferred embodiment shown in FIG. 3, there arefirst and second circuit board units 20 that are identical inconstruction. Each of the first and second circuit board units 2P has abottom surface formed with a die-receiving cavity 20P, a top surfaceformed with a bore 21P to access the die-receiving cavity 20P, and aplurality of contact pads 22P on the top surface. Each of the first andsecond circuit boardunits 2P is further formed with a plurality ofelectroplated holes 23P registered respectively with the contact pads22P and extending through the bottom surface thereof. The lead frame 5is placed between the first and second circuit board units 2P. Each oftwo conductive contact layers 51 is disposed between the lead frame 5and a respective one of the first and second circuit board units 2P tobond the leads 50 on the lead frame 5 onto respective ones of theelectroplated holes 23P to establish electrical connection withcorresponding ones of the contact pads 22P.

[0060]FIG. 18 is illustrates the sixteenth preferred embodiment of thisinvention, which is based on the fifth preferred embodiment. In FIG. 18,unlike the fifth preferred embodiment shown in FIG. 6, there are firstand second circuit board units 2Q that are identical in construction.Each of the first and second circuit board units 2Q has a top surfaceformed with a die-receiving cavity 20Q and a plurality of contact pads22Q, and a plurality of electroplated holes 23Q that are registeredrespectively with the contact pads 22Q and that extend through a bottomsurface thereof. The lead frame 5 is placed between the first and secondcircuit board units 2P. Each of two conductive contact layers 51 isdisposed between the lead frame 5 and a respective one of the first andsecond circuit board units 2P to bond the leads 50 on the lead frame 5onto respective ones of the electroplated holes 23P to establishelectrical connection with corresponding ones of the contact pads 22P.

[0061]FIG. 19 is illustrates the seventeenth preferred embodiment ofthis invention, which is based on the eleventh preferred embodiment. InFIG. 19, unlike the eleventh preferred embodiment shown in FIG. 13, thecircuit boardunit 2R is further formed with a plurality of electroplatedholes 23R registered respectively with the contact pads 22R andextending through a bottom surface of the circuit board unit 2R. Thelead frame 5 is placed below the circuit board unit 2R. The conductivecontact layer 51 is disposed between the lead frame 5 and the circuitboard unit 2R to bond the leads 50 onthe lead frame 5 onto theelectroplated holes 23R to establish electrical connection withcorresponding ones of the contact pads 22R. FIG. 20 is illustrates theeighteenth preferred embodiment of this invention, which is based on theseventeenth preferred embodiment. In FIG. 20, unlike the seventeenthpreferred embodiment shown in FIG. 19, there are first and secondcircuit board units 2S that are identical in construction. Each of thefirst and second circuit board units 2S is formed with a plurality ofelectroplated holes 23S registered respectively with the contact pads22S and extending through a bottom surface thereof. The lead frame 5 isplaced between the first and second circuit board units 2S. Each of twoconductive contact layers 51 is disposed between the lead frame 5 and arespective one of the first and second circuit board units 2S to bondthe leads 50 on the lead frame 5 onto respective ones of theelectroplated holes 23S to establish electrical connection withcorresponding ones of the contact pads 22S.

[0062]FIG. 21 illustrates the nineteenth preferred embodiment of thisinvention, which is based on the thirteenth preferred embodiment. InFIG. 21, unlike the thirteenth preferred embodiment shown in FIG. 15,the circuit board unit 2T is further formed with a plurality ofelectroplated holes 23T registered respectively with the contact pads22T and extending through a bottom surface of the circuit board unit 2T.The lead frame 5 is placed below the circuit board unit 2T. Theconductive contact layer 51 is disposed between the lead frame 5 and thecircuit board unit 2T to bond the leads 50 on the lead frame 5 onto theelectroplated holes 23T to establish electrical connection withcorresponding ones of the contact pads 22T.

[0063]FIG. 22 is illustrates the twentieth preferred embodiment of thisinvention, which is based on the nineteenth preferred embodiment. InFIG. 22, unlike the nineteenth preferred embodiment shown in FIG. 19,there are first and second circuit board units 2U that are identical inconstruction. Each of the first and second circuit board units 2U isformed with a plurality of electroplated holes 23U registeredrespectively with the contact pads 22U and extending through a bottomsurface thereof. The lead frame 5 is placed between the first and secondcircuit board units 2U. Each of two conductive contact layers 51 isdisposed between the lead frame 5 and a respective one of the first andsecond circuit board units 2U to bond the leads 50 on the lead frame 5onto respective ones of the electroplated holes 23U to establishelectrical connection with corresponding ones of the contact pads 22U.

[0064]FIG. 23 illustrates the twenty-first preferred embodiment of thisinvention. In this embodiment, a circuit board unit 2V has a top surfaceformed with a bore 21V and a plurality of contact pads 22V. A die 3 hasan upper surface provided with a plurality of solder pads 30. The die 3is attached to a bottom surface of the circuit board unit 2V by anadhesive layer 27 such that the solder pads 30 on the die 3 are exposedvia the bore 21V in the circuit board unit 2V. A plurality of conductivewires 4 extend through the bore 21V and wire-bond the solder pads 30 tothe contact pads 22V. A lead frame 5 is placed on top of the circuitboard unit 2V and has a plurality of leads 50. A conductive contactlayer 51 bonds the leads 50 on the lead frame 5 onto corresponding onesof the contact pads 22V. Finally, a plastic protective layer 6 is usedto encapsulate the circuit board unit 2V and at least a portion of thelead frame 5.

[0065]FIG. 24 illustrates the twenty-second preferred embodiment of thisinvention, which is based on the twenty-first preferred embodiment. InFIG. 24, unlike the twenty-first preferred embodiment shown in FIG. 23,the circuit board unit 2W further has opposite side portions formed witha plurality of positioning notches 26W that correspond respectively tothe contact pads 22W. Each of the leads 50 on the lead frame 5 has oneend inserted into a respective one of the positioning notches 26W. Aconductive contact layer 51 is used to bond the leads 50 on the leadframe 5 onto corresponding ones of the contact pads 22W.

[0066]FIG. 25 illustrates the twenty-third preferred embodiment of thisinvention, which is based on the twenty-first preferred embodiment. InFIG. 25, unlike the twenty-first preferred embodiment shown in FIG. 23,the circuit board unit 2X is further formed with a plurality ofelectroplated holes 23X registered respectively with the contact pads22X and extending through a bottom surface of the circuit board unit 2X.The lead frame 5 is placed below the circuit board unit 2X. Theconductive contact layer 51 is disposed between the lead frame 5 and thecircuit board unit 2X to bond the leads 50 on the lead frame 5 onto theelectroplated holes 23X to establish electrical connection withcorresponding ones of the contact pads 22X.

[0067]FIG. 26 illustrates the twenty-fourth preferred embodiment of thisinvention, which is based on the twenty-third preferred embodiment. InFIG. 26, unlike the twenty-third preferred embodiment shown in FIG. 25,there are first and second circuit board units 2Y that are identical inconstruction. Each of the first and second circuit board units 2Y isformed with a plurality of electroplated holes 23Y registeredrespectively with the contact pads 22Y and extending through a bottomsurface thereof. The lead frame 5 is placed between the first and secondcircuit board units 2Y. Each of two conductive contact layers 51 isdisposed between the lead frame 5 and a respective one of the first andsecond circuit board units 2Y to bond the leads 50 on the lead frame 5onto respective ones of the electroplated holes 23Y to establishelectrical connection with corresponding ones of the contact pads 22Y.

[0068] While the present invention has been described in connection withwhat is considered the most practical and preferred embodiments, it isunderstood that this invention is not limited to the disclosedembodiments but is intended to cover various arrangements includedwithin the spirit and scope of the broadest interpretation so as toencompass all such modifications and equivalent arrangements.

I claim:
 1. A method for fabricating an integrated circuit chip,comprising: (a) forming a circuit board unit with a die-receiving cavityat a bottom surface of the circuit board unit, a bore to access thedie-receiving cavity at a top surface of the circuit board unit, and aplurality of contact pads on the top surface of the circuit board unit;(b) forming a die having an upper surface provided with a plurality ofsolder pads; (c) placing the die in the die-receiving cavity such thatthe solder pads on the die are exposed via the bore in the circuit boardunit; (d) wire-bonding the solder pads to the contact pads by means ofconductive wires that extend through the bore; (e) placing a lead frameon top of the circuit board unit, and bonding leads on the lead frameonto corresponding ones of the contact pads via a conductive contactlayer; and (f) forming a plastic protective layer to encapsulate thecircuit board unit and at least a portion of the lead frame.
 2. Themethod of claim 1 , wherein the conductive contact layer used in step(e) is formed from a silver epoxy.
 3. The method of claim 1 , whereinthe conductive contact layer used in step (e) is formed from solderpaste.
 4. The method of claim 1 , wherein, in step (a), the circuitboard unit includes a lower circuit board formed with the die-receivingcavity; and an upper circuit board superimposed on the lower circuitboard and formed with the bore, the upper circuit board being formedwith first electroplated holes registered respectively with the contactpads, the lower circuit board being formed with second electroplatedholes registered respectively with the first electroplated holes.
 5. Amethod for fabricating an integrated circuit chip, comprising: (a)forming a circuit board unit with a die-receiving cavity and a pluralityof contact pads on a top surface of the circuit board unit; (b) forminga die having an upper surface provided with a plurality of solder pads;(c) placing the die in the die-receiving cavity such that the solderpads on the die are exposed from the die-receiving cavity; (d)wire-bonding the solder pads to the contact pads by means of conductivewires; (e) placing a lead frame on top of the circuit board unit, andbonding leads on the lead frame onto corresponding ones of the contactpads via a conductive contact layer; and (f) forming a plasticprotective layer to encapsulate the circuit board unit and at least aportion of the lead frame.
 6. The method of claim 5 , wherein theconductive contact layer used in step (e) is formed from a silver epoxy.7. The method of claim 5 , wherein the conductive contact layer used instep (e) is formed from solder paste.
 8. The method of claim 5 ,wherein, in step (a), the circuit board unit includes a lower circuitboard and an upper circuit board superimposed on the lower circuit boardand formed with the die-receiving cavity, the upper circuit board beingformed with first electroplated holes registered respectively with thecontact pads, the lower circuit board being formed with secondelectroplated holes registered respectively with the first electroplatedholes.
 9. A method for fabricating an integrated circuit chip,comprising: (a) forming a circuit board unit with at least twodie-receiving cavities at a bottom surface of the circuit board unit, atleast two bores to access a respective one of the die-receiving cavitiesat a top surface of the circuit board unit, and a plurality of contactpads on the top surface of the circuit board unit; (b) forming at leasttwo dies, each having an upper surface provided with a plurality ofsolder pads; (c) placing each of the dies in a respective one of thedie-receiving cavities such that the solder pads on each of the dies areexposed via a respective one of the bores in the circuit board unit; (d)wire-bonding the solder pads to the contact pads by means of conductivewires that extend through the bores; (e) placing a lead frame on top ofthe circuit board unit, and bonding leads on the lead frame ontocorresponding ones of the contact pads on edge portions of the circuitboard unit via a conductive contact layer; and (f) forming a plasticprotective layer to encapsulate the circuit board unit and at least aportion of the lead frame.
 10. The method of claim 9 , wherein theconductive contact layer used in step (e) is formed from a silver epoxy.11. The method of claim 9 , wherein the conductive contact layer used instep (e) is formed from solder paste.
 12. A method for fabricating anintegrated circuit chip, comprising: (a) forming a circuit board unitwith at least two die-receiving cavities and a plurality of contact padsat a top surface of the circuit board unit; (b) forming at least twodies, each having an upper surface provided with a plurality of solderpads; (c) placing each of the dies in a respective one of thedie-receiving cavities such that the solder pads on each of the dies areexposed from the respective one of the die receiving cavities; (d)wire-bonding the solder pads to the contact pads by means of conductivewires; (e) placing a lead frame on top of the circuit board unit, andbonding leads on the lead frame onto corresponding ones of the contactpads on edge portions of the circuit board unit via a conductive contactlayer; and (f) forming a plastic protective layer to encapsulate thecircuit board unit and at least a portion of the lead frame.
 13. Themethod of claim 12 , wherein the conductive contact layer used in step(e) is formed from a silver epoxy.
 14. The method of claim 12 , whereinthe conductive contact layer used in step (e) is formed from solderpaste.
 15. A method for fabricating an integrated circuit chip,comprising: (a) forming a first circuit board unit with a firstdie-receiving cavity at a bottom surface of the first circuit boardunit, a first bore to access the first die-receiving cavity at a topsurface of the first circuit board unit, a plurality of first contactpads on the top surface of the first circuit board unit, and a pluralityof first electroplated holes that are registered respectively with thefirst contact pads and that extend through the bottom surface of thefirst circuit board unit; (b) forming a first die having an uppersurface provided with a plurality of first solder pads; (c) placing thefirst die in the first die-receiving cavity such that the first solderpads on the first die are exposed via the first bore in the firstcircuit board unit; (d) wire-bonding the first solder pads to the firstcontact pads by means of first conductive wires that extend through thefirst bore; (e) placing a lead frame below the first circuit board unit,and bonding leads on the lead frame onto the first electroplated holesto establish electrical connection with corresponding ones of the firstcontact pads via a first conductive contact layer; and (f) forming aplastic protective, layer to encapsulate the first circuit board unitand at least a portion of the lead frame.
 16. The method of claim 15 ,wherein the conductive contact layer used in step (e) is formed from asilver epoxy.
 17. The method of claim 15 , wherein the conductivecontact layer used in step (e) is formed from solder paste.
 18. Themethod of claim 15 , further comprising, prior to step (f): forming asecond circuit board unit with a second die-receiving cavity at a bottomsurface of the second circuit board unit, a second bore to access thesecond die-receiving cavity at a top surface of the second circuit boardunit, a plurality of second contact pads on the top surface of thesecond circuit board unit, and a plurality of second electroplated holesthat are registered respectively with the second contact pads and thatextend through the bottom surface of the second circuit board unit;forming a second die having an upper surface provided with a pluralityof second solder pads; placing the second die in the seconddie-receiving cavity such that the second solder pads on the second dieare exposed via the second bore in the second circuit board unit;wire-bonding the second solder pads to the second contact pads by meansof second conductive wires that extend through the second bore; and withthe read frame disposed between the first and second circuit boardunits, bonding the leads on the lead frame onto the second electroplatedholes to establish electrical connection with corresponding ones of thesecond contact pads via a second conductive contact layer.
 19. Amethodfor fabricating an integrated circuit chip, comprising: (a) forming afirst circuit board unit with a first die-receiving cavity and aplurality of first contact pads on a top surface of the first circuitboard unit, and a plurality of first electroplated holes that areregistered respectively with the first contact pads and that extendthrough a bottom surface of the first circuit board unit; (b) forming afirst die having an upper surface provided with a plurality of firstsolder pads; (c) placing the first die in the first die-receiving cavitysuch that the first solder pads on the first die are exposed from thefirst die-receiving cavity; (d) wire-bonding the first solder pads tothe first contact pads by means of first conductive wires; (e) placing alead frame below the first circuit board unit, and bonding leads on thelead frame onto the first electroplated holes to establish electricalconnection with corresponding ones of the first contact pads via a firstconductive contact layer; and (f) forming a plastic protective layer toencapsulate the first circuit board unit and at least a portion of thelead frame.
 20. The method of claim 19 , wherein the conductive contactlayer used in step (e) is formed from a silver epoxy.
 21. The method ofclaim 19 , wherein the conductive contact layer used in step (e) isformed from solder paste.
 22. The method of claim 19 , furthercomprising, prior to step (f): forming a second circuit board unit witha second die-receiving cavity and a plurality of second contact pads ona top surface of the second circuit board unit, and a plurality ofsecond electroplated holes that are registered respectively with thesecond contact pads and that extend through a bottom surface of thesecond circuit board unit; forming a second die having an upper surfaceprovided with a plurality of second solder pads; placing the second diein the second die-reeiving cavity such that the second solder pads onthe second die are exposed from the second die-receiving cavity;wire-bonding the second solder pads to the second contact pads by meansof second conductive wires; and with the lead frame disposed between thefirst and second circuit board units, bonding the leads on the leadframe onto the second electroplated holes to establish electricalconnection with corresponding ones of the second contact pads via asecond conductive contact layer.
 23. A method for fabricating anintegrated circuit chip, comprising: (a) forming a circuit board unitwith a die-receiving cavity at a bottom surface of the circuit boardunit, a bore to access the die-receiving cavity at a top surface of thecircuit board unit, a plurality of contact pads on the top surface ofthe circuit board unit, and a plurality of positioning notches that aredisposed on opposite side portions of the circuit board unit and thatcorrespond respectively to the contact pads; (b) forming a die having anupper surface provided with a plurality of solder pads; (c) placing thedie in the die-receiving cavity such that the solder pads on the die areexposed via the bore in the circuit board unit; (d) wire-bonding thesolder pads to the contact pads by means of conductive wires that extendthrough the bore; (e) inserting one end of each of a plurality of leadsof a lead frame into a respective one of the positioning notches, andbonding the leads on the lead frame onto corresponding ones of thecontact pads via a conductive contact layer; and (f) forming a plasticprotective layer to encapsulate the circuit board unit and at least aportion of the lead frame.
 24. The method of claim 23 , wherein theconductive contact layer used in step (e) is formed from a silver epoxy.25. The method of claim 23 , wherein the conductive contact layer usedin step (e) is formed from solder paste.
 26. The method of claim 23 ,wherein, in step (a), the circuit board unit includes a lower circuitboard formed with the die-receiving cavity, and an upper circuit boardsuperimposed on the lower circuit board and formed with the bore, theupper circuit board being formed with first electroplated holesregistered respectively with the contact pads, the lower circuit boardbeing formed with second electroplated holes registered respectivelywith the first electroplated holes.
 27. A method for fabricating anintegrated circuit chip, comprising: (a) forming a circuit board unitwith a die-receiving. cavity and a plurality of contact pads on a topsurface of the circuit board unit, and a plurality of positioningnotches that are disposed on opposite side portions of the circuit boardunit and that correspond respectively to the contact pads; (b) forming adie having an upper surface provided with a plurality of solder pads;(c) placing the die in the die-receiving cavity such that the solderpads on the die are exposed from the die-receiving cavity; (d)wire-bonding the solder pads to the contact pads by means of conductivewires; (e) inserting one end of each of a plurality of leads of a leadframe into a respective one of the positioning notches, and bonding theleads on the lead frame onto corresponding ones of the contact pads viaa conductive contact layer; and (f) forming a plastic protective layerto encapsulate the circuit board unit and at least a portion of the leadframe.
 28. The method of claim 27 , wherein the conductive contact layerused in step (e) is formed from a silver epoxy.
 29. The method of claim27 , wherein the conductive contact layer used in step (e) is formedfrom solder paste.
 30. The method of claim 27 , wherein, in step (a),the circuit board unit includes a lower circuit board, and an uppercircuit board superimposed on the lower circuit board and formed withthe die-receiving cavity, the upper circuit board being formed withfirst electroplated holes registered respectively with the contact pads,the lower circuit board being formed with second electroplated holesregistered respectively with the first electroplated holes.
 31. A methodfor fabricating an integrated circuit chip, comprising: (a) forming acircuit board unit with at least two die-receiving cavities at a bottomsurface of the circuit board unit, at least two bores to access arespective one of the die-receiving cavities at a top surface of thecircuit board unit, a plurality of contact pads on the top surface ofthe circuit board unit, and a plurality of positioning notches that aredisposed on opposite side portions of the circuit board unit and thatcorrespond respectively to the contact pads; (b) forming at least twodies, each having an upper surface provided with a plurality of solderpads; (c) placing each of the dies in a respective one of thedie-receiving cavities such that the solder pads on each of the dies areexposed via a respective one of the bores in the circuit board unit; (d)wire-bonding the solder pads to the contact pads by means of conductivewires that extend through the bores; (e) inserting one end of each of aplurality of leads of a lead frame into a respective one of thepositioning notches, and bonding the leads on the lead frame ontocorresponding ones of the contact pads via a conductive contact layer;and (f) forming a plastic protective layer to encapsulate the circuitboard unit and at least a portion of the lead frame.
 32. The method ofclaim 31 , wherein the conductive contact layer used in step (e) isformed from a silver epoxy.
 33. The method of claim 31 , wherein theconductive contact layer used in step (e) is formed from solder paste.34. A method for fabricating an integrated circuit chip, comprising: (a)forming a circuit board unit with at least two die-receiving cavitiesand a plurality of contact pads at a top surface of the circuit boardunit, and a plurality of positioning notches that are disposed onopposite side portions of the circuit board unit and that correspondrespectively to the contact pads; (b) forming at least two dies, eachhaving an upper surface provided with a plurality of solder pads; (c)placing each of the dies in a respective one of the die-receivingcavities such that the solder pads on each of the dies are exposed fromthe respective one of the die receiving cavities; (d) wire-bonding thesolder pads to the contact pads by means of conductive wires; (e)inserting one end of each of a plurality of leads of a lead frame into arespective one of the positioning notches, and bonding the leads on thelead frame onto corresponding ones of the contact pads via a conductivecontact layer; and (f) forming a plastic protective layer to encapsulatethe circuit board unit and at least a portion of the lead frame.
 35. Themethod of claim 34 , wherein the conductive contact layer used in step(e) is formed from a silver epoxy.
 36. The method of claim 34 , whereinthe conductive contact layer used in step (e) is formed from solderpaste.
 37. An integrated circuit chip comprising: a circuit board unithaving a bottom surface formed with a die-receiving cavity, a topsurface formed with a bore to access said die-receiving cavity, and aplurality of contact pads on said top surface of said circuit boardunit; a die having an upper surface provided with a plurality of solderpads, said die being placed inside said die-receiving cavity such thatsaid solder pads are exposed via said bore in said circuit board unit; aplurality of conductive wires that extend through said bore and thatwire-bond said solder pads to said contact pads; a lead frame placed ontop of said circuit board unit, said lead frame having a plurality ofleads; a conductive contact layer disposed between said lead frame andsaid circuit board unit to bond said leads on said lead frame ontocorresponding ones of said contact pads; and a plastic protective layerto encapsulate said circuit board unit and at least a portion of saidlead frame.
 38. The integrated circuit chip of claim 37 , wherein saidconductive contact layer is formed from a silver epoxy.
 39. Theintegrated circuit chip of claim 37 , wherein said conductive contactlayer is formed from solder paste.
 40. The integrated circuit chip ofclaim 37 , wherein said circuit board unit includes a lower circuitboard formed with said die-receiving cavity, and an upper circuit boardsuperimposed on said lower circuit board and formed with said bore, saidupper circuit hoard being formed with first electroplated holesregistered respectively with said contact pads, said lower circuit boardbeing formed with second electroplated holes registered respectivelywith said first electroplated holes.
 41. An integrated circuit chipcomprising: a circuit board unit having a top surface formed with adie-receiving cavity and a plurality of contact pads; a die having anupper surface provided with a plurality of solder pads, said die beingplaced in said die-receiving cavity such that said solder pads areexposed from said die-receiving cavity; a plurality of conductive wiresfor wire-bonding said solder pads to said contact pads; a lead frameplaced on top of said circuit board unit, said lead frame having aplurality of leads; a conductive contact layer disposed between saidlead frame and said circuit board unit to bond said leads on said leadframe onto corresponding ones of said contact pads; and a plasticprotective layer to encapsulate said circuit board unit and at least aportion of said lead frame.
 42. The integrated circuit chip of claim 41, wherein said conductive contact layer is formed from a silver epoxy.43. The integrated circuit chip of claim 41 , wherein said conductivecontact layer is formed from solder paste.
 44. The integrated circuitchip of claim 41 , wherein said circuit board unit includes a lowercircuit board and an upper circuit board superimposed on said lowercircuit board and formed with said die-receiving cavity, said uppercircuit board being formed with first electroplated holes registeredrespectively with said contact pads, said lower circuit board beingformed with second electroplated holes registered respectively with saidfirst electroplated holes.
 45. An integrated circuit chip comprising: acircuit board unit having a bottom surface formed with at least twodie-receiving cavities, and a top surface formed with at least two boresto access a respective one of said die-receiving cavities and furtherformed with a plurality of contact pads; at least two dies, each havingan upper surface provided with a plurality of solder pads, each of saiddies being placed in a respective one of said die-receiving cavitiessuch that said solder pads on each of said dies are exposed via arespective one of said bores in said circuit board unit; a plurality ofconductive wires that extend through said bores and that wire-bond saidsolder pads to said contact pads; a lead frame placed on top of saidcircuit board unit, said lead frame having a plurality of leads; aconductive contact layer disposed between said lead frame and saidcircuit board unit to bond said leads on said lead frame ontocorresponding ones of said contact pads; and a plastic protective layerto encapsulate said circuit board unit and at least a portion of saidlead frame.
 46. The integrated circuit chip of claim 45 , wherein saidconductive contact layer is formed from a epoxy.
 47. The integratedcircuit chip of claim 45 , wherein said conductive contact layer isformed from solder paste.
 48. An integrated circuit chip comprising: acircuit board unit having a top surface formed with at least twodie-receiving cavities and a plurality of contact pads; at least twodies, each having an upper surface provided with a plurality of solderpads, each of said dies being placed in a respective one of saiddie-receiving cavities such that said solder pads on each of said diesare exposed from the respective one of said die receiving cavities; aplurality of conductive wires that wire-bond said solder pads to saidcontact pads; a lead frame placed on top of said circuit board unit,said lead frame having a plurality of leads; a conductive contact layerthat bonds said leads on said lead frame onto corresponding ones of saidcontact pads; and a plastic protective layer to encapsulate said circuitboard unit and at least a portion of said lead frame.
 49. The integratedcircuit chip of claim 48 , wherein said conductive contact layer isformed from a silver epoxy.
 50. The integrated circuit chip of claim 48, wherein said conductive contact layer is formed from solder paste. 51.An integrated circuit chip comprising: a first circuit board unit havinga bottom surface formed with a first die-receiving cavity, a top surfaceformed with a first bore to access said first die-receiving cavity andfurther formed with a plurality of first contact pads, and a pluralityof first electroplated holes that are registered respectively with saidfirst contact pads and that extend through said bottom surface of saidfirst circuit board unit; a first die having an upper surface providedwith a plurality of first solder pads, said first die being placed insaid first die-receiving cavity such that said first solder pads on saidfirst die are exposed via said first bore in said first circuit boardunit; a plurality of first conductive wires that extend through saidfirst bore and that wire-bond said first solder pads to said firstcontact pads; a lead frame placed below said first circuit board unit,said lead frame having a plurality of leads; a first conductive contactlayer to bond said leads on said lead frame onto said firstelectroplated holes to establish electrical connection withcorresponding ones of said first contact pads; and a plastic protectivelayer to encapsulate said first circuit board unit and at least aportion of said lead frame.
 52. The integrated circuit chip of claim 51, wherein said conductive contact layer is formed from a silver epoxy.53. The integrated circuit chip of claim 51 , wherein said conductivecontact layer is formed from solder paste.
 54. The integrated circuitchip of claim 51 , further comprising: a second circuit board unithaving a bottom surface formed with a second die-receiving cavity, a topsurface formed with a second bore to access said second die-receivingcavity and further formed with a plurality of second contact pads, and aplurality of second electroplated holes that are registered respectivelywith said second contact pads and that extend through said bottomsurface of said second circuit board unit, said lead frame beingdisposed between said first and second circuit board units; a second diehaving an upper surface provided with a plurality of second solder pads,said second die being placed in said second die-receiving cavity suchthat said second solder pads are exposed via said second bore in saidsecond circuit board unit; a plurality of second conductive wires thatextend through said second bore and that wire-bond said second solderpads to said second contact pads; and a second conductive contact layerto bond said leads on said lead frame onto said second electroplatedholes to establish electrical connection with corresponding ones of saidsecond contact pads.
 55. An integrated circuit chip comprising: a firstcircuit board unit having a top surface formed with a firstdie-receiving cavity and a plurality of first contact pads, and aplurality of first electroplated holes that are registered respectivelywith said first contact pads and that extend through a bottom surface ofsaid first circuit board unit; a first die having an upper surfaceprovided with a plurality of first solder pads, said first die beingplaced in said first die-receiving cavity such that said first solderpads are exposed from said first die-receiving cavity; a plurality offirst conductive wires that wirebond said first solder pads to saidfirst contact pads; a lead frame placed below said first circuit boardunit, said lead frame having a plurality of leads; a first conductivelayer to bond said leads on said lead frame onto said firstelectroplated holes to establish electrical connection withcorresponding ones of said first contact pads; and a plastic protectivelayer to encapsulate said first circuit board unit and at least aportion of said lead frame.
 56. The integrated circuit chip of claim 55, wherein said conductive contact layer is formed from a silver epoxy.57. The integrated circuit chip of claim 55 , wherein said conductivecontact layer is formed from solder paste.
 58. The integrated circuitchip of claim 55 , further comprising: a second circuit board unithaving a top surface formed with a second die-receiving cavity and aplurality of second contact pads, and a plurality of secondelectroplated holes that are registered respectively with said secondcontact pads and that extend through a bottom surface of said secondcircuit board unit, said lead frame being disposed between said firstand second circuit board units; a second die having an upper surfaceprovided with a plurality of second solder pads, said second die beingplaced in said second die-receiving cavity such that said second solderpads are exposed from said second die-receiving cavity; a plurality ofsecond conductive wires to wire-bond said second solder pads to saidsecond contact pads; and a second conductive contact layer to bond saidleads on said lead frame onto said second electroplated holes toestablish electrical connection with corresponding ones of said secondcontact pads.
 59. An integrated circuit chip comprising: a circuit boardunit having a bottom surface formed with a die-receiving cavity, a topsurface formed with a bore to access said die-receiving cavity andfurther formed with a plurality of contact pads, and opposite sideportions formed with a plurality of positioning notches that correspondrespectively to said contact pads; a die having an upper surfaceprovided with a plurality of solder pads, said die being placed in saiddie-receiving cavity such that said solder pads are exposed via saidbore in said circuit board unit; a plurality of conductive wires thatextend through said bore and that wire-bond said solder pads to saidcontact pads; a lead frame having a plurality of leads, one end of eachof said leads being inserted into a respective one of said positioningnotches; a conductive contact layer to bond said leads on said leadframe onto corresponding ones of said contact pads adjacent to said sideportions of said circuit board unit; and a plastic protective layer toencapsulate said circuit board unit and at least a portion of said leadframe.
 60. The integrated circuit chip of claim 59 , wherein saidconductive contact layer is formed from a silver epoxy.
 61. Theintegrated circuit chip of claim 59 , wherein said conductive contactlayer is formed from solder paste.
 62. An integrated circuit chipcomprising: a circuit board unit having a top surface formed with adie-receiving cavity and a plurality of contact pads, and opposite sideportions formed with a plurality of positioning notches that correspondrespectively to said contact pads; a die having an upper surfaceprovided with a plurality of solder pads, said die being placed in saiddie-receiving cavity such that said solder pads on said die are exposedfrom said die-receiving cavity; a plurality of conductive wires thatwire-bond said solder pads to said contact pads; a lead frame having aplurality of leads, one end of each of said leads being inserted into arespective one of said positioning notches; a conductive contact layerto bond said leads on said lead frame onto corresponding ones of saidcontact pads adjacent to said opposite side portions of said circuitboard unit; and a plastic protective layer to encapsulate said circuitboard unit and at least a portion of said lead frame.
 63. The integratedcircuit chip of claim 62 , wherein said conductive contact layer isformed from a silver epoxy.
 64. The integrated circuit chip of claim 62, wherein said conductive contact layer is formed from solder paste. 65.An integrated circuit chip comprising: a circuit board unit having abottom surface formed with at least two die-receiving cavities, a topsurface formed with at least two bores to access a respective one ofsaid die-receiving cavities and further formed with a plurality ofcontact pads, and opposite side portions formed with a plurality ofpositioning notches that correspond respectively to said contact pads;at least two dies, each having an upper surface provided with aplurality of solder pads, each of said dies being placed in a respectiveone of said die-receiving cavities such that said solder pads on each ofsaid dies are exposed via a respective one of said bores in said circuitboard unit; a plurality of conductive wires that extend through saidbores and that wire-bond said solder pads to said contact pads; a leadframe having a plurality of leads, one end of each of said leads beinginserted into a respective one of said positioning notches; a conductivecontact layer to bond said leads on said lead frame onto correspondingones of said contact pads adjacent to said side portions of said circuitboard unit; and a plastic protective layer to encapsulate said circuitboard unit and at least a portion of said lead frame.
 66. The integratedcircuit chip of claim 65 , wherein said conductive contact layer isformed from a silver epoxy.
 67. The integrated circuit chip of claim 65, wherein said conductive contact layer is formed from solder paste. 68.An integrated circuit chip comprising: a circuit board unit having a topsurface formed with at least two die-receiving cavities and a pluralityof contact pads, and opposite side portions formed with a plurality ofpositioning notches that correspond respectively to said contact pads;at least two dies, each having an upper surface provided with aplurality of solder pads, each of said dies being placed in a respectiveone of said die-receiving cavities such that said solder pads on each ofsaid dies are exposed from the respective one of said die-receivingcavities; a plurality of conductive wires that wire-bond said solderpads to said contact pads; a lead frame having a plurality of leads, oneend of each of said leads being inserted into a respective one of saidpositioning notches; a conductive contact layer to bond said leads onsaid lead frame onto corresponding ones of said contact pads adjacent tosaid opposite side portions of said circuit board unit; and a plasticprotective layer to encapsulate said circuit board unit and at least aportion of said lead frame.
 69. The integrated circuit chip of claim 68, wherein said conductive contact layer is formed from a silver epoxy.70. The integrated circuit chip of claim 68 , wherein said conductivecontact layer is formed from solder paste.
 71. A method of fabricatingan integrated circuit chip, comprising: (a) forming a circuit board unitwith a bore, and a plurality of contact pads on a top surface of thecircuit board unit; (b) forming a die having an upper surface providedwith a plurality of solder pads; (c) attaching the die onto a bottomsurface of the circuit board unit such that the solder pads on the dieare exposed via the bore in the circuit board unit; (d) wire-bonding thesolder pads to the contact pads by means of conductive wires that extendthrough the bore; (e) placing a lead frame on top of the circuit boardunit, and bonding leads on the lead frame onto corresponding ones of thecontact pads via a conductive contact layer; and (f) forming a plasticprotective layer to encapsulate the circuit board unit and at least aportion of the lead frame.
 72. The method of claim 71 , wherein theconductive contact layer used in step (e) is formed from a silver epoxy.73. The method of claim 71 , wherein the conductive contact layer usedin step (e) is formed from solder paste.
 74. A method of fabricating anintegrated circuit chip, comprising: (a) forming a first circuit boardunit with a first bore, a plurality of first contact pads on a topsurface of the first circuit-board unit, and a plurality of firstelectroplated holes that are registered respectively with the firstcontact pads and that extend through a bottom surface of the firstcircuit board unit; (b) forming a first die having an upper surfaceprovided with a plurality of first solder pads; (c) attaching the firstdie onto the bottom surface of the first circuit board unit such thatthe first solder pads are exposed via the first bore in the firstcircuit board unit; (d) wire-bonding the first solder pads to the first5 contact pads by means of first conductive wires that extend throughthe first bore; (e) placing a lead frame below the first circuit boardunit, and bonding leads on the lead frame onto the first electroplatedholes to establish electrical connection with corresponding ones of thefirst contact pads via a first conductive contact layer; and (f) forminga plastic protective layer to encapsulate the first circuit board unitand at least a portion of the lead frame.
 75. The method of claim 74 ,wherein the first conductive contact layer used in step (e) is formedfrom a silver epoxy.
 76. The method of claim 74 , wherein the firstconductive contact layer used in step (e) is formed from solder paste.77. The method of claim 74 , further comprising, prior to step (f):forming a second circuit board unit with a second bore, a plurality ofsecondcontactpadsonatopsurface of the second circuit board unit, and aplurality of second electroplated holes that are registered respectivelywith the second contact pads and that extend through a bottom surface ofthe second circuit board unit; forming a second die having an uppersurface provided with a plurality of second solder pads; attaching thesecond die onto the bottom surface of the second circuit board unit suchthat the second solder pads are exposed via the second bore in thesecond circuit board unit; wire-bonding the second solder pads to thesecond contact pads by means of second conductive wires that extendthrough the second bore; and with the lead frame between the first andsecond circuit board units, bonding the leads on the lead frame onto thesecond electroplated holes to establish electrical connection withcorresponding ones of the second contact pads via a second conductivecontact layer.
 78. A method of fabricating an integrated circuit chip,comprising: (a) forming a circuit board unit with a bore, a plurality ofcontact pads on a top surfaceof the, circuit board unit, and a pluralityof positioning notches that are disposed on opposite side portions ofthe circuit board unit dnd that correspond respectively to the contactpads; (b) forming a die having an upper surface provided with aplurality of solder pads; (c) attaching the die onto a bottom surface ofthe circuit board unit such that the solder pads on the die are exposedvia the bore in the circuit board unit; (d) wire-bonding the solder padsto the contact pads by means of conductive wires that extend through thebore; (e) inserting one end of each of a plurality of leads of a leadframe into a respective one of the positioning notches, and bonding theleads on the lead frame onto corresponding ones of the contact padsadjacent to the opposite side portions of the circuit board unit via aconductive contact layer; and (f) forming a plastic protective layer toencapsulate the circuit board unit and at least a portion of the leadframe.
 79. The method of claim 78 , wherein the conductive contact layerused in step (e) is formed from a silver epoxy.
 80. The method of claim78 , wherein the conductive contact layer used in step (e) is formedfrom solder paste.
 81. An integrated circuit chip comprising: a circuitboard unit having a top surface formed with a bore and a plurality ofcontact pads; a die having an upper surface provided with a plurality ofsolder pads, said die being attached to a bottom surface of said circuitboard unit such that said solder pads on said die are exposed via saidbore in said circuit board unit; a plurality of conductive wires thatextend through said bore and that wire-bond said solder pads to saidcontact pads; a lead frame placed on top of said circuit board unit,said lead frame having a plurality of leads; a conductive contact layerthat bonds said leads on said lead frame onto corresponding ones of saidcontact pads; and a plastic protective layer to encapsulate said circuitboard unit and at least a portion of said lead frame.
 82. The integratedcircuit chip of claim 81 , wherein said conductive contact layer isformed from a silver epoxy.
 83. The integrated circuit chip of claim 81, wherein said conductive contact layer is formed from solder paste. 84.An integrated circuit chip, comprising: a first circuit-board unithaving a first bore, a top surface formed with a plurality of firstcontact pads, and a plurality of first electroplated holes that areregistered respectively with said first contact pads and that extendthrough a bottom surface of said first circuit board unit; a first diehaving an upper surface provided with a plurality of first solder pads,said first die being attached onto the bottom surface of said firstcircuit board unit such that said first solder pads are exposed via saidfirst bore in said first circuit board unit; a plurality of firstconductive wires that extend through said first bore and that wire-bondsaid first solder pads to said first contact pads; a lead frame placedbelow said first circuit board unit, said lead frame having a pluralityof leads; a first conductive contact layer to bond said leads on saidlead frame onto said first electroplated holes to establish electricalconnection with corresponding ones of said first contact pads; and aplastic protective layer to encapsulate said first circuit board unitand at least a portion of said lead frame.
 85. The integrated circuitchip of claim 84 , wherein said first conductive contact layer is formedfrom a silver epoxy.
 86. The integrated circuit chip of claim 84 ,wherein said first conductive contact layer is formed from solder paste.87. The integrated circuit chip of claim 84 , further comprising: asecond circuit board unit having a second bore, a top surface formedwith a plurality of second contact pads, and a plurality of secondelectroplated holes that are registered respectively with said secondcontact pads and that extend through a bottom surface ofsaidsecondcircuitboardunit, saidleadframebeing disposed between saidfirst and second circuit board units; a second die having an uppersurface provided with a plurality of second solder pads, said second diebeing attached onto the bottom surface of said second circuit board unitsuch that said second solder pads are exposed via said second bore insaid second circuit board unit; a plurality of second conductive wiresthat extend through said second bore and that wire-bond said secondsolder pads to said second contact pads; and a second conductive contactlayer to bond said leads on said lead frame onto said secondelectroplated holes to establish electrical connection withcorresponding ones of said second contact pads.
 88. An integratedcircuit chip comprising: a circuit board unit having a bore, a topsurface formed with a plurality of contact pads, and opposite sideportions formed with a plurality of positioning notches that correspondrespectively to said contact pads; a die having an upper surfaceprovided with a plurality of solder pads, said die being attached onto abottom surface of said circuit board unit such that said solder pads onsaid die are exposed via said bore in said circuit board unit; aplurality of conductive wires that extend through said bore and thatwire-bond said solder pads to said contact pads; a lead frame having aplurality of leads, one end of each of said leads being inserted into arespective one of said positioning notches; a conductive contact layerthat bonds said leads on said lead frame onto corresponding ones of saidcontact pads adjacent to said opposite side portions of said circuitboard unit; and a plastic protective layer to encapsulate said circuitboard unit and at least a portion of said lead frame.
 89. The integratedcircuit chip of claim 88 , wherein said conductive contact layer isformed from a silver epoxy.
 90. The integrated circuit chip of claim 88, wherein said conductive contact layer is formed from solder paste.